Quite often, low frequency switches must be designed or configured with other circuitry in order to be compatible with either TTL or CMOS logic. Accordingly, these devices must be capable of operating at typical TTL and CMOS voltage levels (i.e., 0.5/4.5 volts). Susceptibility to DC bias ripple must be minimized in order to assure that the signals passing through these switches are subject to minimal amplitude modulation which can result from the ripple voltage.
Two major transistor topologies are currently used for low frequency (DC to 6 GHz) switches The first topology is the series-shunt FET switch. This type of switch operates with negative control voltages. Thus, in order to interface with standard TTL or CMOS logic, a buffer is required since typical TTL and CMOS voltage levels are positive. Further, the current series-shunt topology is sensitive to DC bias ripple. The second topology currently used is the PIN diode technology. PIN diode switches will operate at standard TTL and CMOS logic levels, but require current drivers to source enough current for proper operation. The PIN diode topology is also susceptible to signal problems associated with DC bias ripple.
Therefore, a need has arisen for a transistor switch topology which may be efficiently utilized with TTL and CMOS logic and which is less sensitive to DC bias ripple than existing topologies. A need has further arisen to provide a switching topology which does not require additional buffers or current drivers in order to be compatible with TTL or CMOS logic.